FPGA - RoboCop

To run the assembler, use "python src.s dest.hex" for an output. To run the verilog program on an FPGA, an altera cyclone 10 is required. Then after bootloading the Arduino vidor chip, we were able to upload a bit stream using Quartus Prime.

* What did you plan on doing?

We were planning to make a robot with a custom architecture to control PWM, real-time data, use SDRAM, control motors, assembler, multithreading and maybe PID with floating point.

* What did you end up doing?

We ended up doing PWM, building a pipelined CPU, building an HBridge, using embedded memory blocks, controlling LEDS and motors, messing with PLL, figuring out how to run/use quartus prime, reading so much documentation, and building our hardware.

* What did you learn?

I learned how complicated SDRAM was and how it worked with respect to its steps, delays, and state machine for memory controllers. I also learned how System PLL worked for controlling frequency. I learned how to use an FPGA and the differences in Verilog structure and code. We had to figure out the pins communication and how to read schematics. Finally, we learned a lot of circuitry/physics along with how to build a robot.

Requires Python 3 or greater. Tested with Python 3.7

Assembler Usage

Python 3

python3 <assembly_input>.s <hex_output>.hex
                    

Note: del requires 3 digits, mot/led requires 1 digits, movl/movh requires 2 digits.

Robot ISA

                    mot port, mode [0000]
                    HEX: 0xPM
                    BIN: 0000 xxxx pppp mmmm
                    p = <port>
                    m = <mode>
                    
                    
                    movl val, dest [0010]
                    HEX: 2IIR
                    BIN: 0010 iiii iiii rrrr
                    i = <info>
                    r = <reg>
                    
                    movh val, dest [0111]
                    HEX: 7IIR
                    BIN: 0111 iiii iiii rrrr
                    i = <info>
                    r = <reg>
                    
                    cpy src, dest [0101]
                    HEX: 9xSD
                    BIN: 0101 xxxx ssss dddd
                    s = <src reg>
                    d = <dest reg>
                    
                    # Jumps 
                    jmp loc [0001][0000]
                    HEX: 10Lx
                    BIN: 0001 0000 llll xxxx
                    l = <location reg>
                    
                    jz cmp, loc [0001][0001]
                    HEX: 11CL
                    BIN: 0001 0001 cccc llll
                    c = <compare reg>
                    l = <location reg>
                    
                    jns ... [0001][0010]
                    HEX: 12CL
                    BIN: 0001 0010 cccc llll
                    c = <compare reg>
                    l = <location reg>
                    
                    jnz ... [0001][0011]
                    HEX: 13CL
                    BIN: 0001 0011 cccc llll
                    c = <compare reg>
                    l = <location reg>
                    
                    js ... [0001][0100]
                    HEX: 14CL
                    BIN: 0001 0100 cccc llll
                    c = <compare reg>
                    l = <location reg>
                    
                    led port, mode [0011]
                    HEX: 3xPM
                    BIN: 0011 xxxx pppp mmmm
                    p = <port>
                    m = <mode>
                    
                    del sec [0100]
                    HEX: 8TTT
                    BIN: 1000 tttt tttt tttt
                    t = <time>
                    
                    nop
                    HEX: FFFF
                    BIN: 1111 1111 1111 1111
                    sub regA, regB, dest
                    
                    subtract
                    HEX: CABD
                    BIN: 1100 aaaa bbbb dddd
                    a = <reg a>
                    b = <reg b>
                    d = <dest>
                    
                    add regA, regB, dest
                    HEX: DABD
                    BIN: 1101 aaaa bbbb dddd
                    a = <reg a>
                    b = <reg b>
                    d = <dest>
                    
                    mul regA, regB, dest
                    HEX: EABD
                    BIN: 1110 aaaa bbbb dddd
                    a = <reg a>
                    b = <reg b>
                    d = <dest>
                    
                    AAAA - halt
                    
                    // NOT DOING
                    loop time [0101][0000]
                    endl [0101][0001]
                    
                    halt - invalid instruction
                    secs/time: fixed point only